3 State and Open Collector Devices  

Table 20     TTL OutPut Signal Characteristics

Introduction
    The emphasis to this point has been to learn some fundamental ideas about digital devices and how they can be applied to control situations of interest to Mechanical and Chemical Engineers.  The 8255 interface was introduced to suggest the availability of new and clever interface devices.  However, little attention has been spent on the types of possible output signals TTL devices produce. Of course the quick response is TTL devices output Logic "0" and Logic "1" and these logic signals correspond to 0 volts and 5 volts, respectively.  This is generally a correct answer but the 3 state device and the open collector device are important exceptions and illustrate the extra detail that must be mustered when it really gets down to designing a practical control scheme.

    The 3 state and open collector devices are commonly classified as TTL (transistor, transistor logic) device because of the types input signals they accept not the types of output signals they generate.  A "normal" TTL device has input pins that accept 5V and 0V signals to initiate the performance of an internal task and then produce a 5V or a 0V signal to be delivered to its output pins.  The open collector and 3 state devices do accept the 0V or the 5V signal like "normal" TTL devices but have different output signal characteristics.  It is this difference in output signal that makes them so important for control applications.  Historically, the open collector device was developed before the 3 state device and it will be discussed first.

The NPN Transistor

    To appreciate the way an open collector device functions it is useful to first review the operation of the NPN transistor and its role in generating the output signals for a "normal" TTL device.  Figure 12.1 shows a symbolic diagram of a NPN transistor connected between a 5 volt power supply and a light emitting diode, an LED.  This LED is shown with its cathode attached to ground and arrows suggesting light beams placed near the diode symbol.

    Figure 12.1 labels the three parts of the transistor, i.e. the base, the collector and the emitter, as B, C and E, respectively.  From our perspective as TTL device users, the only significant idea to learn about the NPN transistor is the fact that the continuity of the circuit path from the point (x) in the diagram through the point (y) to the positive terminal, the anode, of the diode at point (z) depends on the voltage applied to the base.  ( This really is a gross simplification but it will do for now!)

    With these labels in mind consider the example circuit in Figure 12.1.  If there is a 5 volt signal on the base of this NPN transistor there is a continuous path for electrons to flow from the ground through the diode past point (z) (y) and (x) and into the positive terminal of the 5 volt power supply. If there is a 0 volt signal on the base, then the path from point (x) through point (y) to point (z) is broken and there is no way for electrons to travel from the ground through the LED to the 5 volt power supply.

    Because the above explanation of how a NPN transistor works is so naive, the end result is very simple but for TTL logic devices and other NPN transistor switching applications very true.

If there is a 5 volt signal on the base of a NPN transistor there is a continuity path for electron current to travel from the NPN's emitter terminal to its collector terminal.  If there is a 0 volt signal on the base than current will not travel from emitter to collector terminals.

    In other words, the NPN transistor base connection behaves like a switch for the circuit connected through the NPN's emitter and collector terminals.  For the application shown in Figure 12.1, the LED will light if there is 5 volts on the NPN's base terminal. The LED will go off when a 0 volt signal is applied to the base terminal.

Digital Devices with TTL Outputs

    To emphasize the role of the open collector digital device it is important to understand the electrical characteristics of the "normal" TTL device. Figure 12.2 shows both a "normal" and an open collector TTL device.  Figure 12.2A has four NPN transistors in it and represents a "normal" TTL device.  One of these transistors is easily identified as being different from the other three. It has two emitter pins labeled Input A and Input B.  This dual emitter NPN transistor is located on the upper left part of the figure.  The other three transistors have single emitters and are part of the TTL device's output circuitry.  Our attention will initially be focused on the transistor that is circled near the center of the diagram.  From Figure 12.1 it should be clear that the labels (x), (y) and (z) emphasize the conducting path through the transistor and that the signal on the base decides if point (x) is electrically connected to point (z) or not.

    Consider the two possible voltages for the base connection on the circled transistor in Figure 12.2A.  If that base is at 5 volts then there is an electrical path from point (x) to point (z) on the diagram. therefore, there is a path from point (x) through resistor R₄ to the ground connection also shown in the diagram.  Under these conditions, the voltage value at point (x) is less than 5 volts and the voltage on the emitter terminal is significantly above 0 volts.  (The actual voltage values can be determined if the values of R₂ and R₄ and the small voltage drop through the transistor were stated.)   If the circled transistor's base is at 0 volts there is no conducting path from point (x) to point (z). The voltage at point (x) is almost 5 volts and the voltage on the emitter terminal is almost 0V.

    It is not necessary to know the value of the resistors in Figure 12.2A, to explain how this normal TTL output pin gets its 0V or 5V signal.  When there is a 5 volt signal on the base of the transistor in the circle, the voltage x the base of transistor Q₄, i.e. the transistor inclosed in the rectangle, is not high enough to allow current to pass through the path that contains resistor R₃. However, because of the design of transistor Q₃, the voltage at the base of Q₃ is sufficient to permit current to flow between the TTL output pin and the ground connection.

    When there is a 0 volt signal on the base of the transistor in the circle in Figure 12.2A, the electrical connection from point (x) to point (z) is broken and the voltage at the base of Q₄ is almost 5 volts.  This allows Q₄ to provide an electrical connection from the 5 volt power pin through R₃ to the TTL output pin.   Thus the output voltage on a "normal" TTL device is determined by the logic on the circled transistor's base.  When this base is at 5 volts the "normal" output pin is at 0 volts but if the base voltage changes to 0 volts then the "normal" output pin is at the 5 volt logic 1 state.

TTL Devices with Open Collector Outputs

    Figure 12.2B shows a schematic diagram of an open collector TTL device. This device contains only three NPN transistors.  The input signals for this open collector device affect the performance of the two emitter transistor which in turn determines what voltage is delivered to the base of the transistor, Q₂, in the middle of the diagram. It should be apparent that the NPN transistor that is missing is the one that provides the 5 volt signal path from the power pin to the output pin of the device.  Therefore, even though there are two possible signals at the base of the circled transistor, Q₂, there is only one possible voltage signal at the output pin.  When a 5 volt signal is on the base of Q₂, that transistor allows current to flow from the 5 volt power supply through R₂ and R₄ to ground. If the values of these two resistors are selected carefully, there will be sufficient voltage at the base of Q₃ to make the path between the output pin and the ground pin conducting.  Thus the output pin assume the same voltage value as the ground pin. It will be at 0 Volts.

    If the base of the circled _{transistor, Q2}, in Figure 12.2B is at 0V then there is no conducting path to R₄ and the base of Q₃ is at 0 volts.  Under these conditions, the is no conducting path between the output pin and the ground pin of the device.  In fact, the output pin has no conducting path to any part of the circuit. It is just like a wire hanging out the window with nothing connected on either end but you can only see the end that is hanging out the window.

     This condition of a wire not being connected to a real voltage signal is called the logic "nothing" state.  It means just that! There is no electrical voltage associated with the wire and that wire has nothing to do with the circuit.  The difference between a TTL device with a normal output and an a TTL device with an open collector output is summarized in Table 20.  It is also emphasized in the following example.

The 7405 Open Collector Invertor

    Consider the 7404 and the 7405 TTL packages. Both have 6 invertors, both have the same pinout and both do not work correctly unless pin 14 is at 5 volts and pin 7 is at 0 volts.  So what is the difference?  As you have guessed, the 7404 is a TTL device with normal outputs while the 7405 TTL device has open collector outputs.  It is constructive to compare the characteristics of the invertor output pin signals for both of these TTL devices when TTL logic signals are applied to pin 1 of either package.  ( Pin 1 of the 7404 and the 7405 is an input to an invertor while pin 2 is that invertor's output pin.)

    If you put a 0 volt signal on pin 1 of a 7404 you expect to get a 5 volt signal out of pin 2. Likewise, if the device is functioning properly, a 0 volt signal on pin 1 of a 7404 will generate a 5 volt signal from pin 2.  This is not exactly what happens with the 7405 even though pin 1 is the input pin of the first invertor in the package and pin 2 is its output.  If you put a 5 V signal into pin 1 of a 7405 you will get the expected 0 volt signal out of pin 2.  However, a 0 volt signal at pin 1 does NOT produce a 5 volt signal at pin 2. In fact there is no electrical signal on pin 2 at all.  Under these conditions pin 2 is not connected to any circuit inside the 7405.  It is as if the wire was just stuck into the 7475's plastic case but not connected to anything inside that case, i.e the logic "nothing" state.

The 3 State Device

    Compared to the TTL device with open collector outputs, the TTL device with 3 state outputs is a new invention.  Figure 12.3 has a diagram that provides the general characteristics of a 3 state TTL invertor.  The striking visual distinction between these chips and the 7404 or 7405 is the addition of the enable pins.  Each enable pin functions in the expected way by controlling the operation of its corresponding invertor.  Consider the 74126 three state device.  Output Q₁ will not respond to input D₁ unless pin E₁ is at 5 volts. For the 74125 three state invertor, Q₁ will not respond to an input signal at D₁ unless pin E₁ is at 0 volts.

    The striking mental difference between the two 3 state devices in Figure 12.3 and the 7404 or 7405 is also very obviously associated with the addition of a third possible output state.  When either 3 state device in the diagram is enabled the output signals are the opposite of the corresponding input signals. If D₁ is at 0 volts then Q₁ is at 5 volts. If D₁ is at five volts then Q₁ is at zero volts.  Nothing is new here!  However, when a 3 state invertor is disabled, ie. 0 volts on E₁ in the 74126 or 5 volts on E₁ on in the 74125, then both Q₁ outputs are now at the logic "nothing" state.  The same would be true of Q₂ with respect to E₂ or any other corresponding invertor Q pin to E pin combination.

Chapter Overview

Review Questions

12.1 Review Figure 12.1 and notice the details of the NPN transistor diagram.  The PNP transistor is another popular transistor that is similar but not identical to the NPN.   Draw function diagram for a PNP transistor.

12.2 Examine Figure 12.2. Draw a "normal TTL Device

12.3 Examine Figure 12.2. Draw an open collector TTL device

12.4 What does TTL stand for?

12.5 Reexamine Figures 12.3 and 8.4.
    a) What 3 state device is most likely shown in Figure 8.4?

    b) If B_Hex is the pattern on the 7475 output pins, what will be the pattern in Hex on the output
         pins of the three state shown in Figure 8.4 when the CPU delivers pulse "b"?

12.6 Examine Figure 11.3. The 75491 at the top of the diagram is not a 3 state device. diagram.
    a) What type of I/O port is the 75491 associated with?
    b) What type of I/O port is associated with a 3 state device?
    c) Why one type of I/O port but not the other?